Semiconductor device, method of adjusting load capacitance for the same, and semiconductor system including the same

ABSTRACT

A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) to KoreanPatent Application No. 10-2010-0089746 filed on Sep. 14, 2010, thedisclosure of which is incorporated by reference in its entirety herein.

BACKGROUND

1. Technical Field

Embodiments of the present inventive concept relate to a semiconductordevice, and more particularly, to a semiconductor device for adjusting aload capacitance of a complementary bit line of a bit line senseamplifier, a method of adjusting the load capacitance of thecomplementary bit line, and a semiconductor system including thesemiconductor device.

2. Discussion of Related Art

A bit line sense amplifier senses and amplifies a voltage differencebetween a bit line and a complimentary bit line of a memory cell. Layoutmethods for a memory cell array including a bit line sense amplifierinclude an open bit line method and a folded bit line method. The openbit line method allows a memory cell to be disposed at each intersectionof a plurality of word lines and a plurality of bit lines, therebyminimizing chip area. In addition, the open bit line method allows a bitline sense amplifier to sense and amplify the voltage difference betweena bit line and a complementary bit line, which are respectivelyconnected to different memory cells, which are respectively connected todifferent word lines. However, in the resulting layout produced by theopen bit line method, half of the bit lines at the edge of the memorycell array are dummy bit lines.

SUMMARY

An exemplary embodiment of the present inventive concept includes asemiconductor device for adjusting a load capacitance of a complementarybit line connected to a bit line sense amplifier to be the same orsubstantially the same as the load capacitance of a bit line connectedto the bit line sense amplifier. An exemplary embodiment of theinventive concept includes a method of adjusting the load capacitance ofthe complementary bit line. An exemplary embodiment of the inventiveconcept includes at least one semiconductor system including thesemiconductor device. The semiconductor device or the method may reducea sensing loss of the bit line sense amplifier.

According to an exemplary embodiment of the present inventive concept, asemiconductor device includes a bit line, a complementary bit line, asense amplifier configured to sense and amplify a voltage differencebetween the bit line and the complementary bit line, and a capacitanceadjusting circuit configured to adjust a load capacitance of thecomplementary bit line in response to a plurality of control signals.

The capacitance adjusting circuit may include a plurality of adjustingblocks connected between the complementary bit line and a ground andcapacitances of the respective adjusting blocks may be adjusted based onthe control signals, respectively.

Alternatively, the capacitance adjusting circuit may include a pluralityof capacitors; and a plurality of switches connected between thecomplementary bit line and the respective capacitors to respectivelyconnect the capacitors to the complementary bit line in response to theplurality of control signals, respectively.

The capacitors may have different capacitances. Each of the capacitorsmay include at least one sub capacitor connected in series. The at leastone sub capacitor may be connected to one another through at least oneamong a first connecting means and a second connecting means.

The semiconductor may further include a mode register set or a pluralityof fuse circuits configured to generate the plurality of control signalsfor adjusting the load capacitance of the complementary bit line to bethe same or substantially the same as a load capacitance of the bitline. The sense amplifier may have an open bit line architecture.

According to an exemplary embodiment of the present inventive concept, amethod of adjusting a load capacitance of a complementary bit line of asense amplifier in a semiconductor device includes generating aplurality of control signals and adjusting capacitance of each of aplurality of adjusting blocks connected between the complementary bitline and a ground based on a corresponding one of the control signals.The generating the plurality of control signals may include generatingthe plurality of control signals using a mode register set.

When each of the adjusting blocks includes a switch and at least onecapacitor connected in series, the switch may control a connectionbetween the complementary bit line and the at least one capacitor basedon a corresponding one of the control signals.

According to an exemplary embodiment of the present inventive concept, amemory system may include the above-described semiconductor device and aprocessor configured to control operations of the semiconductor device.

According to an exemplary embodiment of the inventive concept, a memorymodule may include the above-described semiconductor device and asemiconductor substrate on which the semiconductor device is mounted.

According to an exemplary embodiment of the inventive concept, in asemiconductor system that includes the above-described memory module,the system includes a socket into which the memory module is inserted,and a processor configured to control operations of the semiconductordevice mounted on the memory module through the socket.

According to an exemplary embodiment of the inventive concept, asemiconductor device includes a sense amplifier (e.g., a bit line senseamplifier) and an adjusting block. The sense amplifier senses andamplifies a voltage difference between a bit line and a complimentarybit line. The bit line and complimentary bit lines may be connected to asame word line. The adjusting block is configured to output an adjustingsignal to the complimentary bit line in response to a control signal.The adjusting block includes a transistor having a first non-gateterminal connected to the complimentary bit line and a second non-gateterminal, a conductive material overlapping with a portion of acapacitive material, and at least one metal contact. One end of a firstpart of the capacitive material receives a ground voltage and the otherend is connected to the second non-gate terminal, and a second part ofthe capacitive material is connected to a floating voltage. The at leastone metal contacts are connected to the capacitive material in theportion that does not overlap with the conductive material. The floatingvoltage may prevent the second part of the capacitive material fromfunctioning as a capacitor.

The semiconductor device may further include a second adjusting blockconfigured to output a second adjusting signal to the complimentary bitline in response to a second control signal. The second adjusting blockmay include a second transistor having a third non-gate terminalconnected to the complimentary bit line and a fourth non-gate terminal,a second capacitive material including first, second, third, and fourthportions and a second conductive material overlapping with the first andsecond portions, and first and second metal contacts connected to thethird and fourth portions, respectively. The second portion may beconnected to one of the third and fourth portions. The first portion maybe connected to the fourth non-gate terminal, and the second portion maybe connected to the first portion through the second conductivematerial.

BRIEF DESCRIPTION OF THE DRAWINGS

The present inventive concept will become more apparent by describing indetail exemplary embodiments thereof with reference to the attacheddrawings in which:

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept;

FIG. 2 shows a capacitance adjusting circuit illustrated in FIG. 1according to an exemplary embodiment of the present inventive concept;

FIG. 3 shows the top layer of the capacitance adjusting circuitillustrated in FIG. 2 according to an exemplary embodiment of thepresent inventive concept;

FIG. 4 is a cross-sectional view of a first adjusting block illustratedin FIG. 3 according to an exemplary embodiment of the present inventiveconcept;

FIG. 5 is a cross-sectional view of a second adjusting block illustratedin FIG. 3 according to an exemplary embodiment of the present inventiveconcept;

FIG. 6 is a cross-sectional view of a third adjusting block illustratedin FIG. 3 according to an exemplary embodiment of the present inventiveconcept;

FIG. 7 is a diagram of a memory module including the semiconductordevice illustrated in FIG. 1 according to an exemplary embodiment of thepresent inventive concept;

FIG. 8 is a block diagram of a computer including the memory moduleillustrated in FIG. 7 according to an exemplary embodiment of thepresent inventive concept;

FIG. 9 is a memory system according to an exemplary embodiment of thepresent inventive concept including the semiconductor device illustratedin FIG. 1;

FIG. 10 is a memory system according to an exemplary embodiment of thepresent inventive concept including the semiconductor device illustratedin FIG. 1; and

FIG. 11 is a flowchart of a method of adjusting the load capacitance ofa complementary bit line of a sense amplifier in a semiconductor deviceaccording to an exemplary embodiment of the present inventive concept.

DETAILED DESCRIPTION

The present inventive concept now will be described more fullyhereinafter with reference to the accompanying drawings, in whichexemplary embodiments thereof are shown. The inventive concept may,however, be embodied in many different forms and should not be construedas limited to the exemplary embodiments set forth herein. In thedrawings, the size and relative sizes of layers and regions may beexaggerated for clarity. Like numbers refer to like elements throughout.It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent.

FIG. 1 is a block diagram of a semiconductor device 10 according to anexemplary embodiment of the present inventive concept. The semiconductordevice 10 includes a memory cell array 15, a row decoder 60, a columndecoder 70, and a timing controller 80.

The semiconductor device 10 can adjust the load capacitance or parasiticcapacitance of a complementary bit line #BL. Parasitic capacitance isunwanted capacitance that may be present between circuit componentsmerely due their proximity to one another. The semiconductor device 10may be implemented by volatile or non-volatile memory including a senseamplifier using an open bit line method.

As an example, the volatile memory may be dynamic random access memory(DRAM), static RAM (SRAM), thyristor-RAM (T-RAM), zero-capacitor RAM(Z-RAM), or twin transistor RAM (TTRAM). As an example, the non-volatilememory may be electrically erasable programmable read-only memory(EEPROM), flash memory, ferroelectric RAM (FeRAM), magnetoresistive RAM(MRAM), phase-change RAM (PRAM), resistive RAM (RRAM), or nano-RAM(NRAM). For clarity of the below description, it is assumed that thesemiconductor device 10 is implemented by DRAM, but the inventiveconcept can be applied to both volatile and non-volatile memory devices.

The memory cell array 15 includes a plurality of capacitance adjustingcircuits 100, a plurality of bit line sense amplifiers 30, and aplurality of sub memory cell arrays 50. For clarity of the description,the semiconductor device 10 will be described by explaining an arrayunit 20 illustrated in FIG. 1.

Each sub memory cell array 50 includes a plurality of memory cellsconnected to a word line WL and a plurality of bit lines BL. Each bitline sense amplifier 30 senses and amplifies the difference between avoltage of a bit line BL and a complementary bit line #BL. The bit linesense amplifier 30 may be applied to any semiconductor device, e.g., anyvolatile or non-volatile semiconductor device. The semiconductor devicesmay use an open bit line architecture or an open bit line senseamplification scheme, as an example.

The capacitance adjusting circuit 100 is connected to the complementarybit line #BL and adjusts the load capacitance of the complementary bitline #BL in response to a plurality of control signals Tune1, Tune2, andTune3 output from the timing controller 80. The row decoder 60 decodes arow address XADD received from the timing controller 80 and selects oneof the word lines WL in the sub memory cell array 50 based on a resultof the decoding. The column decoder 70 decodes a column address YADDreceived from the timing generator 80 and selects at least one of thebit lines BL in the sub memory cell array 50 based on a result of thedecoding.

FIG. 2 shows the capacitance adjusting circuit 100 illustrated in FIG. 1according to an exemplary embodiment of the inventive concept. Referringto FIGS. 1 and 2, the capacitance adjusting circuit 100 includes a firstadjusting block 110, a second adjusting block 120, and a third adjustingblock 130.

The first adjusting block 110 includes a first capacitor C1 and a firstswitch T1, which connects the first capacitor C1 to the complementarybit line #BL in response to the first control signal Tune1. The secondadjusting block 120 includes a second capacitor C2 and a third capacitorC3, which are connected in series, and a second switch T2 which connectsthe second capacitor C2 to the complementary bit line #BL in response tothe second control signal Tune2. The third adjusting block 130 includesa fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6,which are connected in series, and a third switch T3 which connects thefourth capacitor C4 to the complementary bit line #BL in response to thethird control signal Tune3. The capacitance of the first through sixthcapacitors C1 through C6 may be the same or different. The switches T1,T2, and T3 may be transistors.

For clarity of the description, the capacitance adjusting circuit 100includes the three adjusting blocks 110, 120, and 130, but the number ofadjusting blocks may be lesser or greater than three (e.g., 1, 2, 4, 5,etc.). In at least one embodiment of the inventive concept, thecapacitances of the adjusting blocks are different from one another. Inat least one embodiment of the inventive concept, each of the switchesT1, T2, and T3 is implemented by a metal-oxide semiconductor (MOS)transistor. However, the inventive concept is not limited thereto, asalternate embodiments of the inventive concept may use a transistor typethat differs from the metal-oxide type.

The control signals Tune1, Tune2, and Tune3 may be generated by thetiming controller 80, as illustrated in FIG. 1, or by a mode registerset (MRS) 150, as illustrated in FIG. 2. While the MRS 150 isillustrated within the capacitance adjusting circuit 100 in FIG. 2, inalternate embodiments, it may be provided outside the capacitanceadjusting circuit 100 or within the timing controller 80. Further, inalternative embodiments, the control signals Tune1, Tune2, and Tune3 maybe generated by a plurality of fuse circuits.

The capacitance adjusting circuit 100 adjusts the load capacitance ofthe complementary bit line #BL in response to the control signals Tune1,Tune2, and Tune3, as shown in Table 1. For ease of discussion, it isassumed that the capacitors C1 through C6 have the same capacitance of 1Cbal and the capacitance of the complementary bit line #BL and thecapacitance of the switches T1 through T3 are not considered.

TABLE 1 Case C total Tune1 Tune2 Tune3 Case1 1/2 Cbal L H L Case2 1/3Cbal L L H Case3 1 Cbal H L L Case4 4/3 Cbal H L H

Referring to Table 1, an ‘H’ indicates a tuning signal is at a logicalhigh level and an ‘L’ indicates that a tuning signal is at logical lowlevel. Case1 shows the capacitance of the complementary bit line #BLadjusted by the second adjusting block 120 when the second controlsignal Tune2 at the high level is applied to the second switch T2 of thesecond adjusting block 120. In other words, the capacitance adjustingcircuit 100 adjusts the load capacitance of the complementary bit line#BL to ½ Cbal, the capacitance of the second adjusting block 120. As aresult, the load capacitance of the bit line BL can be substantially thesame as the load capacitance of the complementary bit line #BL.

Case2 shows the capacitance of the complementary bit line #BL adjustedby the third adjusting block 130 when the third control signal Tune3 atthe high level is applied to the third switch T3 of the third adjustingblock 130. In other words, the capacitance adjusting circuit 100 adjuststhe load capacitance of the complementary bit line #BL to ⅓ Cbal, thecapacitance of the third adjusting block 130. As a result, the loadcapacitance of the bit line BL can be substantially the same as the loadcapacitance of the complementary bit line #BL.

Case3 shows the capacitance of the complementary bit line #BL adjustedby the first adjusting block 110 when the first control signal Tune 1 atthe high level is applied to the first switch T1 of the first adjustingblock 110. In other words, the capacitance adjusting circuit 100 adjuststhe load capacitance of the complementary bit line #BL to 1 Cbal, thecapacitance of the first adjusting block 110. As a result, the loadcapacitance of the bit line BL can be substantially the same as the loadcapacitance of the complementary bit line #BL.

Case4 shows the capacitance of the complementary bit line #BL adjustedby the first and third adjusting blocks 110 and 130 when the first andthird control signals Tune1 and Tune3 at the high level are respectivelyapplied to the first and third switches T1 and T3 of the respectivefirst and third adjusting blocks 110 and 130. In other words, thecapacitance adjusting circuit 100 adjusts the load capacitance of thecomplementary bit line #BL to the sum of 1 Cbal, the capacitance of thefirst adjusting block 110, and ⅓ Cbal, the capacitance of the thirdadjusting block 130. As a result, the load capacitance of the bit lineBL can be substantially the same as the load capacitance of thecomplementary bit line #BL.

While Table 1 shows four exemplary cases, the present invention is notlimited to those cases. For example, the capacitance adjusting circuit100 may adjust the load capacitance of the complementary bit line #BLbased on various combinations of the control signals Tune1, Tune2, andTune3.

As described above, the capacitance adjusting circuit 100 adjusts inresponse to the control signals Tune1, Tune2, and Tune3 so that the loadcapacitance of the complementary bit line #BL and the load capacitanceof the bit line BL are substantially the same, thereby preventing orreducing the sensing loss of the sense amplifier 30. A capacitance beingsubstantially the same as another may indicate that the capacitances arewithin an error tolerance of one another.

FIG. 3 shows the top layer of the capacitance adjusting circuit 100illustrated in FIG. 2 according to an exemplary embodiment of theinventive concept. FIG. 4 is a cross-sectional view of the firstadjusting block 110 illustrated in FIG. 3 according to an exemplaryembodiment of the inventive concept. FIG. 5 is a cross-sectional view ofthe second adjusting block 120 illustrated in FIG. 3 according to anexemplary embodiment of the inventive concept. FIG. 6 is across-sectional view of the third adjusting block 130 illustrated inFIG. 3 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 3, the capacitance adjusting circuit 100 is formed ona layer including a plurality of capacitors SP arranged in a certainpattern. Multiple capacitors SP are connected to one another by a firstconnecting means PP (e.g., a conductor or conductive material) or asecond connecting means SS (e.g., a conductor or conductive material) sothat one or more capacitors (e.g., the capacitor C1, the capacitors C2and C3, and the capacitors C4 through C6) connected in series can beformed for each of the adjusting blocks 110, 120, and 130.

Referring to FIGS. 3 and 4, in the structure of the first adjustingblock 110 of the capacitance adjusting circuit 100, a drain electrode ofthe first switch T1 implemented by a transistor is connected to thecomplementary bit line #BL through a first contact pad PAD1 and a secondcontact pad PAD2. A source electrode of the first switch T1 is connectedto a first electrode of the first capacitor C1 through the first contactpad PAD1, a third contact pad PADS, and a fourth contact pad PAD4. Asecond electrode of the first capacitor C1 is connected to a metalcontact MC formed in the first connecting means PP.

A plurality of contact pads PAD1 through PAD4 are used to electricallyconnect semiconductor elements to one another and are arranged in acertain pattern on the layer on which the capacitance adjusting circuit100 is formed.

A third connecting means M1 (e.g., a conductor or conductive material)may be formed on the metal contact MC to connect the metal contact MC toan external metal line. The third connecting means M1 receives apredetermined voltage from the external metal line and applies thepredetermined voltage to the second electrode of the first capacitor C1.The predetermined voltage received from the external metal line may be aground voltage as an example.

A capacitor SP (e.g., a capacitive material) positioned within the firstconnecting means PP is floated and does not function as a capacitor. Ametal contact MC is connected to each of capacitors SP that arepositioned outside the first connecting means PP so that parasiticcapacitance may be reduced or eliminated. Accordingly, only the firstswitch T1 and the first capacitor C1 are present in the first adjustingblock 110.

Referring to FIGS. 3 and 5, in the structure of the second adjustingblock 120 of the capacitance adjusting circuit 100, the connectionbetween drain and source electrodes of the second switch T2 implementedby a transistor is similar to that of the first switch T1 illustrated inFIG. 4.

A second electrode of the second capacitor C2 is connected to a firstelectrode of the third capacitor C3 through a first connecting means PP.A metal contact MC is connected to each of capacitors SP that arepositioned outside the first connecting means PP so that parasiticcapacitance may be reduced or eliminated.

A second electrode of the third capacitor C3 is connected to a metalcontact MC through a fourth contact pad PAD4, a third contact pad PAD3,and a second connecting means SS. Accordingly, only the second switch T2and the second and third capacitors C2 and C3 connected in series arepresent in the second adjusting block 120.

Referring to FIGS. 3 and 6, in the structure of the third adjustingblock 130, the connection between drain and source electrodes of thethird switch T3 implemented by a transistor is similar to that of thefirst switch T1 illustrated in FIG. 4.

A second electrode of the fourth capacitor C4 is connected to a firstelectrode of the fifth capacitor C5 through a first connecting means PP.A second electrode of the fifth capacitor C5 is connected to a firstelectrode of the sixth capacitor C6 through fourth contact pad PAD4, athird contact pad PAD3, and a second connecting means SS.

A second electrode of the sixth capacitor C6 is connected to a metalcontact MC through a first connecting means PP formed on the sixthcapacitor C6. Each of capacitors SP outside the first connecting meansPP is connected to a metal contact MC so that parasitic capacitance maybe reduced or eliminated. Accordingly, only the third switch T3 and thefourth through sixth capacitors C4 through C6 connected in series arepresent in the third adjusting block 130.

FIG. 7 is a diagram of a memory module 200 including the semiconductordevice 10 illustrated in FIG. 1. Referring to FIG. 7, the memory module200 includes a semiconductor substrate 210 and a plurality ofsemiconductor devices 10 mounted on the semiconductor substrate 210. Thestructure and the operations of the semiconductor devices 10 aresubstantially the same as those of the semiconductor device 10 describedwith reference to FIGS. 1 through 6.

The memory module 200 may also include a controller 230 controlling theoperations of the semiconductor devices 10, respectively. As an example,the memory module 200 may be implemented by a single in-line memorymodule (SIMM) or a dual in-line memory module (DIMM).

FIG. 8 is a block diagram of a computer 300 including the memory module200 illustrated in FIG. 7. The memory system 300 may be implemented by acomputer system. The memory system 300 includes a main board 240, a slot250 mounted on the main board 240, the memory module 200 inserted intothe slot 250, and a processor, e.g., a chip-set 270, controlling theoperations of the semiconductor devices 10 mounted on the memory module200, respectively.

The chip-set 270 may exchange data with the semiconductor devices 10through a data bus. The memory system 300 may be implemented on apersonal computer (PC), a tablet PC, or a notebook computer.

FIG. 9 is a memory system 400 according to an exemplary embodiment ofthe present inventive concept including the semiconductor device 10illustrated in FIG. 1. Referring to FIG. 9, the memory system 400 may beimplemented by a cellular phone, a smart phone, or a wireless Internetdevice. The memory system 400 includes the semiconductor device 10 and aprocessor 410 controlling the data processing operations of thesemiconductor device 10. Data stored in the semiconductor device 10 maybe controlled by the processor 410 to be displayed through a display420.

The memory system 400 may also include a radio transceiver 430, whichtransmits or receives radio signals through an antenna ANT. The radiotransceiver 430 may convert radio signals received through the antennalANT into signals that can be processed by the processor 410. Theprocessor 410 may process the signals output from the radio transceiver430 and store the processed signals in the semiconductor device 10 ordisplay them through the display 420. The radio transceiver 430 may alsoconvert signals output from the processor 410 into radio signals andoutput them through the antenna ANT.

The memory system 400 may also include an input device 440, whichenables control signals to be input for controlling the operations ofthe processor 410 or input data to be processed by the processor 410. Asan example, the input device 440 may be implemented by a pointing devicesuch as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 410 may control the display 420 to display data outputfrom the semiconductor device 10, data output from the radio transceiver430, or data output from the input device 440.

FIG. 10 is a memory system 500 according to an exemplary embodiment ofthe present inventive concept including the semiconductor device 10illustrated in FIG. 1. The memory system 500 may be implemented by adata processing device such as a tablet computer, a net-book, ane-reader, a personal digital assistant (PDA), a portable multimediaplayer (PMP), an MP3 player, or an MP4 player. The memory system 500includes the semiconductor device 10 and a processor 510 controlling thedata processing operations of the semiconductor device 10.

The processor 510 may display data stored in the semiconductor device 10through a display 530 in response to an input signal generated by aninput device 520. As an example, the input device 520 may be implementedby a pointing device such as a touch pad or a computer mouse, a keypad,or a keyboard.

FIG. 11 is a flowchart of a method of adjusting the load capacitance ofthe complementary bit line #BL of a sense amplifier in a semiconductordevice 10 according to an exemplary embodiment of the present inventiveconcept. Referring to FIGS. 2 through 6 and FIG. 11, a capacitorincluding one or more sub capacitors, e.g., the sub capacitor C1, thesub capacitors C2 and C3, or the sub capacitors C4 through C6, which areconnected in series, is formed in each of the adjusting blocks 110, 120,and 130 in the capacitance adjusting circuit 100 in operation S100. Themethod of forming the sub capacitors C1 through C6 has been describedabove with reference to FIGS. 4 through 6.

The switches T1 through T3 are formed in the adjusting blocks 110, 120,and 130, respectively, in operation S120. Source electrodes of therespective switches T1 through T3 are respectively connected to thecapacitors respectively included in the adjusting blocks 110, 120, and130 in operation S140. A drain electrode of each of the switches T1through T3 is connected to the complementary bit line #BL in operationS160.

The control signals Tune1, Tune2, and Tune3 are respectively applied togate electrodes of the respective switches T1 through T3 in operation5200. The control signals Tune1, Tune2, and Tune3 may be generated bythe timing controller 80, the MRS 150, or a plurality of fuse circuits.When each of the control signals Tune1, Tune2, and Tune3 is applied to acorresponding switching among the switches T1 through T3, acorresponding capacitor is connected to the complementary bit line #BL.Accordingly, the load capacitance of the complementary bit line #BL isadjusted by the capacitance adjusting circuit 100.

As described above, according to at least one exemplary embodiment ofthe present inventive concept, the load capacitance of a complementarybit line in a semiconductor device is adjusted, so that the sensing lossof a bit line sense amplifier may be reduced or eliminated.

While the present inventive concept has been particularly shown anddescribed with reference to exemplary embodiments thereof, it will beunderstood by those of ordinary skill in the art that various changes informs and details may be made therein without departing from the spiritand scope of the disclosure.

What is claimed is:
 1. A system including a semiconductor device, thesemiconductor device comprising: a bit line; a complementary bit line; asense amplifier configured to sense and amplify a voltage differencebetween the bit line and the complementary bit line; and a capacitanceadjusting circuit configured to adjust a load capacitance of thecomplementary bit line in response to a plurality of control signals. 2.The system of claim 1, wherein the capacitance adjusting circuitcomprises a plurality of adjusting blocks connected between thecomplementary bit line and a ground and capacitances of the respectiveadjusting blocks are adjusted based on the control signals,respectively.
 3. The system of claim 1, wherein the capacitanceadjusting circuit comprises: a plurality of capacitors; and a pluralityof switches connected between the complementary bit line and therespective capacitors to respectively connect the capacitors to thecomplementary bit line in response to the plurality of control signals,respectively.
 4. The system of claim 3, wherein the capacitors havedifferent capacitances.
 5. The system of claim 3, wherein each of thecapacitors comprises at least one sub capacitor connected in series. 6.The system of claim 5, wherein the at least one sub capacitor isconnected to one another through at least one among a first connectingmeans and a second connecting means.
 7. The system of claim 1, furthercomprising a mode register set (MRS) configured to generate theplurality of control signals for adjusting the load capacitance of thecomplementary bit line to be substantially the same as a loadcapacitance of the bit line.
 8. The system of claim 1, furthercomprising a plurality of fuse circuits configured to generate theplurality of control signals.
 9. The system of claim 1, wherein thesense amplifier is provided in an open bit line architecture.
 10. Thesystem of claim 1, wherein the system is a memory system and furthercomprises a processor configured to control operations of thesemiconductor device.
 11. The system of claim 1, wherein the system is amemory module and further comprises a semiconductor substrate on whichthe semiconductor device is mounted.
 12. The system of claim 11, furthercomprising: a socket into which the memory module is inserted; and aprocessor configured to control operations of the semiconductor devicemounted on the memory module through the socket.
 13. A method ofadjusting a load capacitance of a complementary bit line of a senseamplifier in a semiconductor device, the method comprising: generating aplurality of control signals; and adjusting a capacitance of each of aplurality of adjusting blocks connected between the complementary bitline and a ground based on a corresponding one of the control signals.14. The method of claim 13, wherein the generating the plurality ofcontrol signals comprises generating the plurality of control signalsusing a mode register set.
 15. The method of claim 13, wherein when eachof the adjusting blocks comprises a switch and at least one capacitorconnected in series, the switch controls connection between thecomplementary bit line and the at least one capacitor based on acorresponding one of the control signals.
 16. A semiconductor devicecomprising: a sense amplifier sensing and amplifying a voltagedifference between a bit line and a complimentary bit line; an adjustingblock configured to output an adjusting signal to the complimentary bitline in response to a control signal, wherein the adjusting blockcomprises: a transistor having a first non-gate terminal connected tothe complimentary bit line and a second non-gate terminal; a conductivematerial overlapping with a portion of a capacitive material, whereinone end of a first part of the capacitive material receives a groundvoltage and the other end is connected to the second non-gate terminal,and a second part of the capacitive material is connected to a floatingvoltage; and at least one metal contact connected to the capacitivematerial in the portion that does not overlap with the conductivematerial.
 17. The semiconductor device of claim 16, wherein a gateterminal of the transistor receives the control signal.
 18. Thesemiconductor device of claim 16, wherein the floating voltage preventsthe second part of the capacitive material from functioning as acapacitor.
 19. The semiconductor device of claim 16, further comprising:a second adjusting block configured to output a second adjusting signalto the complimentary bit line in response to a second control signal,wherein the second adjusting block comprises: a second transistor havinga third non-gate terminal connected to the complimentary bit line and afourth non-gate terminal; a second capacitive material including first,second, third, and fourth portions and a second conductive materialoverlaps with the first and second portions, wherein the first portionis connected to the fourth non-gate terminal, and the second portion isconnected to the first portion through the second conductive material;and first and second metal contacts connected to the third and fourthportions, respectively, wherein the second portion is connected to oneof the third and fourth portions.
 20. The semiconductor device of claim19, further comprising a controller configured to output the firstcontrol signal and the second control signal, where the first controlsignal has a logic level that differs from the second control signal.